1. Technical Field
The present invention relates to a fractional Phase Locked Loop (PLL) circuit having a rational number frequency-division ratio.
2. Description of Related Art
Conventionally, a spread spectrum clock generator (SSCG) has been used in high-speed serial communication to prevent a radiated electromagnetic interference. The spread spectrum clock generator is configured to include a fractional PLL circuit having a rational number frequency division ratio.
Generally, the fractional PLL circuit includes a phase frequency comparator, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a phase controller, a phase selection circuit, and a frequency divider.
In the art of the fractional PLL circuit, it has been tried to reduce a jitter in an output-clock signal by changing a phase of a clock pulse through the phase controller and the phase selection circuit (refer to Patent Document 1: JP2012-195824A).
However, the above-described conventional fractional PLL circuit has a problem. The phase controller of the conventional fractional PLL circuit operates at an oscillating frequency of the voltage-controlled oscillator. However, depending on the processing ability of the phase controller, the phase controller cannot operate properly when the oscillating frequency is too high.
In addition, the processing speed of the phase controller cannot meet the oscillating frequency of the voltage-controlled oscillator when the phase controller and the phase selection circuit exchange data therebetween in synchronization with the oscillating frequency of the voltage-controlled oscillator.
It is difficult to reduce the jitter in the output-clock signal when the processing speed of the phase controller cannot meet the oscillating frequency of the voltage-controlled oscillator.